Speaker
Description
SPAD array-based photodetectors are emerging in large-scale photodetector panels because of their appealing characteristics such as compactness, low bias voltages and good photon detection efficiency (PDE). Conventional SiPMs are considered for covering large areas, but the large capacitance of SiPMs brings a serious limitation. They also require an analog readout circuit designed with tradeoffs between power consumption, bandwidth and noise.
To overcome some of the SiPM challenges, this paper presents a photodetection module populated with photon-to-digital converter (PDC) CMOS readout ASICs and tailored for thousands of cm2 up to m2 panels. The prototype that will be presented is a 94 × 74 mm2 module assembled with 8 × 8 PDC readout ASICs. Each ASIC has 4096 individual SPAD readout circuits at 78 μm pitch distributed over a 5 × 5 mm2 area. Each of the 64 ASICs is connected to a tile controller implemented on an external FPGA platform to demonstrate the readout architecture. The tile controller is used to configure, program the PDC bin width (from 10 ns up to μs) for photon counting and send the bin counts to a computer to visualize the data.
The tile controller can implement pulse shape discrimination, dark count mitigation, and time-to-digital converters with sub 100 ps timing resolution. These have been demonstrated on a preliminary 2 × 2 PDC readout ASIC module. We will also discuss the latest measurements on the 8 × 8 PDC tile.
| Your current academic level, | MSc student |
|---|---|
| Your Email | Olivier.Lepage@USherbrooke.ca |
| Affiliation | Université de Shebrooke |
| Supervisor | Serge Charlebois |
| Supervisor Email | serge.charlebois@usherbrooke.ca |
